Intel 65nm and Beyond (or Below): IDF Day 2 Coverage
by Kristopher Kubicki on September 9, 2004 9:26 AM EST- Posted in
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Lithography
Moving to a 65nm transistor requires a 65nm lithography process. We are already seeing devices being built into silicon with features smaller than the wavelength of the light used in the lithography process. As it will be somewhere near 2009 before Intel has their EUV (13nm light wavelength) technology up and running, working with such small features requires some special masking tricks.
At this level, engineers must take into account the fact that light displays properties of both particles and waves. In order to create the situation where a particle of light has a high probability of hitting such a small section of photoresist covered silicon, special masking techniques need to be used to manipulate the wave.
Though it's not the same thing, anyone who has access to a laser can see how a light wave can be manipulated. Just take a piece of paper and cut two vertical slits that are close enough together so as to fit within the radius of the laser pointer beam. Find a dark room, stand a few feet from a wall, and shine your laser through the slits in the paper. What will be seen is a series of vertical lines which represent the interference pattern of the light waves passing through each slit. Well, that's the explanation if we don't try to talk about it on the quantum level.
Using similar properties exhibited by light (though not exactly the same as our example), Intel has devised technology they call Alternating Phase Shift Masks in order to etch extraordinarily small features into a silicon integrated circuit for 65nm fabrication.
Moving to 32nm fabrication, we think Intel will be forced to move to EUV (both the process technology roadmap and the move to 13nm wavelength lithography will occur circa 2009). But until then, and even beyond, advanced masking techniques will enable photolithography to keep up with the ever decreasing size of transistors on silicon.
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drwho9437 - Friday, September 10, 2004 - link
Eskimo I was jus being sloppy in my language. As I progressed. Its good to know I'm not totally nuts. The resists will be a problem because of chain length. I mean for positive resists it seems ovious as it seems to be the ratio of the native to the broken resist chain length that would matter (there solublity). For a negative resist I guess you could somehow have some very simple and short chain somehow but I would think it would still need to be of the order of nm in length. I think it will be interesting if intel or someone else can reach high yeilds on structures of 5-10nm size. That would make SETs or other quantum devices useable in the millions.KristopherKubicki - Friday, September 10, 2004 - link
ceefka: Intel is actually moving in the other direction - particularly for server products. The Memory controller is in fact getting its own tunnel on chipsets like Twin Castle. I suspect this is being done so that they can incorporate multiple memory controllers on a single motherboard.Kristopher
ceefka - Friday, September 10, 2004 - link
Great article, Kristopher.7 + 17 Right on! Seems like all they're doing is shrinking, more cache and pumping the FSB.
Where is that on die memory controller?
It doesn't seem like much of an animal if you keep it in a cage. What they're doing at Intel is great in itself, but it needs something extra.
Eskimo - Thursday, September 9, 2004 - link
#13/#14, You are correct we are now entering the arena where the actual polymer chains which make up our resists are approaching some of the features that are being printed on the wafers. As for etching keep in mind that we don't actually etch the resist. Resist after exposure is developed away in an aqueous solution. The remaining resist serves as a mask for the underlying material either protecting from ion bombardment or etches. The standard etch for today's high aspect ratio features is Reactive Ion Etching (RIE). The 193nm resists in use in leading edge lithography do not have the same etch protection capabilities that were present in DUV(248nm) and i-line(365nm) resists. A new challenge for resists is posed by the upcoming widespread adoption (even Intel might come around) of immersion lithography where the resist will be directly exposed to water in the scanner.As for the article itself, it seems to suggest that Intel came up with the idea of phase shift masks. When in fact they were developed in the late 70's and first put into use in the early 90's by a variety of companies. The only real news on this front is that to reach 65nm on 193nm dry systems you will definately need alternating aperature phase shift masks like the diagram describes which are very costly.
As for the statement saying Intel did not specify what sort of oxide they are doping with carbon for their low-k dielectric it is Silicon Dioxide. Since SiO2 is so prevalent in silicon processing and so well understood we often just refer to it simply as oxide. If it was in fact another material oxidized that would've been specifed (e.g. Aluminum Oxide).
mkruer - Thursday, September 9, 2004 - link
#7 Read again what I wrote, I mentioned nothing abut the SPEED, working faster =! Speed in MHz which you are apparently inferring. I was simply stating that obvious that Intel solution for the majority of its problems is to simple through more cache at it.GodsMadClown - Thursday, September 9, 2004 - link
I remeber going to a talk on the Chandra X-Ray telescope and hearing about all the craziness with mirrors that they had to go through to get the optics to work. I guess that Intel could do the same thing, but It's just getting crazy. No real content, but to make everyone aware that when you deal with EUV radiation, optics get very complex.stephenbrooks - Thursday, September 9, 2004 - link
I'm pretty sure that on the last page it should be "line width" going to 0.7x every two years, not line LENGTH! Total line length on a chip should increase 1.4x every two years because they're packing it in smaller.drwho9437 - Thursday, September 9, 2004 - link
To clarify, I mean you have to etch the resist, dry or wet, you have to do it and that has some limit, but I don't know what it might be or even what kind of etching big fabs use.drwho9437 - Thursday, September 9, 2004 - link
Humm. Aren't we going to hit the limit of resists soon? I mean the resists I know about for ebeam lithography have resolution of something like 8nm. Intel is going to do 23 with photolithography, that's impressive, you can always go to x-rays if all it was was a matter of making the photon wavelength sorter but what about the chemistry? (I'm not a chemist, I'm a physicist/EE)ncage - Thursday, September 9, 2004 - link
I read the other post and thats what i used as my reference to spell it. Dumb idea i guess ;)