Intel 65nm and Beyond (or Below): IDF Day 2 Coverage
by Kristopher Kubicki on September 9, 2004 9:26 AM EST- Posted in
- Trade Shows
Lithography
Moving to a 65nm transistor requires a 65nm lithography process. We are already seeing devices being built into silicon with features smaller than the wavelength of the light used in the lithography process. As it will be somewhere near 2009 before Intel has their EUV (13nm light wavelength) technology up and running, working with such small features requires some special masking tricks.
At this level, engineers must take into account the fact that light displays properties of both particles and waves. In order to create the situation where a particle of light has a high probability of hitting such a small section of photoresist covered silicon, special masking techniques need to be used to manipulate the wave.
Though it's not the same thing, anyone who has access to a laser can see how a light wave can be manipulated. Just take a piece of paper and cut two vertical slits that are close enough together so as to fit within the radius of the laser pointer beam. Find a dark room, stand a few feet from a wall, and shine your laser through the slits in the paper. What will be seen is a series of vertical lines which represent the interference pattern of the light waves passing through each slit. Well, that's the explanation if we don't try to talk about it on the quantum level.
Using similar properties exhibited by light (though not exactly the same as our example), Intel has devised technology they call Alternating Phase Shift Masks in order to etch extraordinarily small features into a silicon integrated circuit for 65nm fabrication.
Moving to 32nm fabrication, we think Intel will be forced to move to EUV (both the process technology roadmap and the move to 13nm wavelength lithography will occur circa 2009). But until then, and even beyond, advanced masking techniques will enable photolithography to keep up with the ever decreasing size of transistors on silicon.
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RyanVM - Thursday, September 9, 2004 - link
I'm trying to figure out if you guys are using "Itanimum" because you're trying to be witty or just don't know that its name is "Itanium". I think my sarcasm meter might be broken.mrmorris - Thursday, September 9, 2004 - link
Interesting article, looking forward to getting "the big picture" when Intel competite technology is included (AMD).PrinceGaz - Thursday, September 9, 2004 - link
1T-SRAM is basically DRAM with a built in controller that handles all the refreshing etc, so it can be used in a similar way to SRAM.Because it uses DRAM technology, its nowhere near as fast as true SRAM and therefore unsuitable for use as cache memory.
Skykat - Thursday, September 9, 2004 - link
As I recall, the Nintendo Gamecube uses 1T-SRAM (1 transistor). Whatever happened to this technology? It would seem a lot more efficient than 6 Transistor SRAM. I think the Gamecube processor was manufactured by IBM though...ncage - Thursday, September 9, 2004 - link
#5 speed is NOT the ideal thing for what itanimum was made for. Itanimum is made for high end servers where caching is just as important as speed. Think of the high end scientific apps where the majority of the work is swapping data back and forth from ram to peform calculations on. Ya they could speed up the cpu but it would be cache starved and would be ide wile it was waiting to fetch data from main memory into cache/registers. Lots of cache is also ideal for large database appliations. One thing i am suprised is intel has not decided to go with an on die memory controller like AMD.mkruer - Thursday, September 9, 2004 - link
When I said double up on the logic I meant parallel processing, not making the logic more complex.mkruer - Thursday, September 9, 2004 - link
I will not say that I am disappointed, but I think I could sum this article up much faster, Intel has Awesome FAB capabilities, but too bad their chip designs are not the greatest. One day Intel might lean that instead of throwing huge amounts of cache to get everything to work faster, to double up on the logic. Just imagine if the Itanimum was cache efficient, with the amount of chip real-estate they could save they could easily double the core logic, and get a true boot in performance.nourdmrolNMT1 - Thursday, September 9, 2004 - link
i agree with number 3.MIKE
CrimsonDeath - Thursday, September 9, 2004 - link
Wow i feel really stupid right now...Johnmcl7 - Thursday, September 9, 2004 - link
Yeah, I fully agree I was a little disappointed the article seemed to end rather abruptly, however it was an interesting read otherwise.Also, shouldn't it be 'extensions of Moore's Law' rather than 'extentions'?
John