Intel 65nm and Beyond (or Below): IDF Day 2 Coverage

Intel 65nm and Beyond (or Below)

Earlier this year we saw our first glimpse at 90nm technology with the launch of Intel's Prescott Pentium 4. Even more recently we have seen 90nm processes show up on server and workstation CPUs, like Nocona. Yet while 90nm processes are just showing up on the market in full force, Intel already has massive plans for pushing technology even farther, with roadmaps ramping to the 32nm stage by 2009. The technologies and strategies to get them there are surprisingly well documented and explained.

The talk of Fall IDF 2004 Day 1 and Day 2 was that of Moore's law; the philosophy put forth that transistor count on a processor doubles every 18 to 24 months. Near the end of our Day 1 Keynote, we got our first look at Montecito, Intel's 90nm IA64 processor with an astounding 24MB of L3 cache. Understanding how Intel is capable of placing 1.72 billion transistors on single chip is certainly a not a simple task; but Intel was kind enough to provide us with a plethora of details on how we can cram billions of transistors on a chip, and how we will continue to uphold Moore's law in the future.

First, a quick look at how Intel has upheld Moore's law:

With the introduction of Montecito, Intel surpassed Moore's law very slightly with massive banks of cache. We will go into more detail about cache and SRAM in a little bit, but in the meantime we have an image of what the processor core actually looks like.