Intel 65nm and Beyond (or Below): IDF Day 2 Coverage

Extensions of Moore's Law

Knowing all of the technical terminology and process information is helpful, but really all of these technologies and advances in production boil down to only a few basic elements that in turn affect Intel's implementation of Moore's law.

With process and lithography size shrinking, every processor family revision provides a 30% reduction in line length.

0.7x line length every 2 years

Adding more layers, decreasing line length and decreasing gate size allows for a 50% reduction in SRAM size every processor family revision.

0.5x SRAM size every 2 years

This conveniently falls in the pattern of processor introduction from Intel for several generations now. Prescott 2M (Pentium 4 6xx) will ship with 2MB L2 cache, Prescott (Pentium 4 5xx) debuted with 1MB L2 cache, Northwood had 512KB L2 and Willamette had 256KB. The 18 month revision between Banias and Dothan also demonstrated a double in cache size. The truth is, Moore's law is in no danger in fading anytime soon - particularly through 2009 where we can continue to expect SRAM sizes to decrease by 50% every two years; thus enabling Intel to place approximately twice as many transistors on a die. Technology like trigrate transistors may even expedite SRAM density with three dimentional gates.

And on that note, we'll end our coverage of the second day of IDF Fall 2004. We still have a few more stops to make, the show floor to cover, another keynote, and AMD to see. Hopefully we will be able to dig up more juicy tidbits of tantalizing tech news for all to feast on. Right now, its time to get in a little breakfast before the next busy day of meetings and sessions begins.