IDF Spring 2005 - Predicting Future CPU Architecture Trends
by Anand Lal Shimpi on March 3, 2005 7:43 PM EST- Posted in
- Trade Shows
We've come across a lot of information about the future of Intel architectures and platforms during these past three days at IDF. We've taken this opportunity to summarize it as best as we can, so let's get started.
More thoughts on Stacked DRAM
Our own Johan De Gelas caught up with Justin Rattner after his keynote to get some more information about stacked die and wafer technology:
1) Current Intel research estimates that about 256MB of memory can be stacked on top of a CPU (die stacking). A huge latency reduction is the result, but if you need more memory you have to go off die of course.
2) Different thermal expansion between the layers might of course ruin the chip. Intel is looking into this but Justin believes that it is not going to stop the stacked die show.
3) Right now stacked die is obviously in its infancy, they still have to move to the next step: one memory chip on top the other.
We're quite excited about the possibility of stacked DRAM although it will definitely be a long time before we see it productized.
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Doormat - Friday, March 4, 2005 - link
I'm thinking its due to the fact that they make their own chipsets. Intel sells chipsets for $40 or so (MCH+ICH), and their uptake on new RAM technologies is quick (well, faster than AMD is, especially with DDR to DDR2). Plus the engineering cost. It doesnt add up. Unless and until they design a new chip from the ground up, an on die memory controller is a lot of work for not a lot of money. Unless they manage to fall far behind AMD in terms of performace, I dont think it'll show up.sprockkets - Friday, March 4, 2005 - link
Gee, let's do everything possible to improve the situation except, oh shit, ditch x86 code that was created around 30 years ago.elecrzy - Friday, March 4, 2005 - link
#6, intel's reasoning doesn't make sense. they seem make people change mobos, not because of differing ram standards, but because they change cpu socket so damn often.mkruer - Friday, March 4, 2005 - link
#7Sure, as if Intels CPU's are not expensive enough, now you want to all another $15 "Integration on die memory controller" tax
bersl2 - Friday, March 4, 2005 - link
You know, I saw enough flashy graphics in three days to make my head spin, and there were enough pictures of the future to make me think this was a World's Fair. Though what can one expect out of an event like this?xsilver - Thursday, March 3, 2005 - link
#6 what you said doesnt make sense from a performance perspective.... how long does it take for new ram standards to come out? there has been sdram (pc66,100,133) ddr ram (pc2100,2700,3200) and now ddr2 (533) oh, and rambus 600,800,1000that's 10 ram standards for pcs as far back as the pentium 200.... the memory controller on the AMD64 has already been updated from HTT800mhz to HTT1000mhz.... and can be continually revised and just introduced on newer steppings of the same cpu's.... eg. amd's forthcoming "e" spec with sse3, 4x ddr3200 support and other stuff for free
and #5 -- LOL -- so true -- AMD mobo's are so cheap, its not funny (not including the nforce4, but thats another issue)
maybe intel could just charge the extra $15 on their cpu's :P
IntelUser2000 - Thursday, March 3, 2005 - link
Well, Intel said they are not supporting integrated memory controller because you have to change the board and the memory and the CPU every time new RAM standards are out. Looking at desktops, that it make sense not to have memory controllers, but for servers they have a solution. Maybe because its more flexible to have a seperate memory controller? I mean you are pretty limited when the memory controller is integrated, in terms of clock speed scaling, increased complexity and memory standards. It makes sense for servers though and Intel recently announced the Xeon MPs and the Itaniums would have common sockets(same sockets) and have integrated memory controller.Anyways this was interesting:
"The answer appears to be somewhere in between Pentium M and Prescott, realistically being much closer to Willamette's 20 stage integer pipeline than Prescott's 31 stage pipe, for strictly power reasons."
See, like I predicted, its best to consume Pentium 4 Northwood and Pentium M together.
mkruer - Thursday, March 3, 2005 - link
#4Na then Intel cant charge and addtional $15 per northbridge chip.
xsilver - Thursday, March 3, 2005 - link
is there a more detailed reason as to WHY intel does not go with the on die memory controller?has AMD patented it and are unwilling to license it?
hasnt the sucess of the amd64 physically shown that the memory controller is highly effective in improving performance?
alangeering - Thursday, March 3, 2005 - link
"Although we're quite convinced that an on-die memory controller would result in the best performance per transistor expended on a new architecture, we're doubtful that Intel would consider one. We may have to wait until stacked die and wafer technology before we see any sort of serious reduction in memory latency through techniques other than more caches and more cores."Well noted, but a little expansion: the latency drop when going to a stacked die/wafer technology comes from 2 things.
1. Proximity to core
2. Intel will have to provide an on-die memory controller... to have an external controller and stacked wafer ram would be poor engineering.
So, expect to see these things together.