Intel Developer Forum Spring 2003 - Day 2: Learn about Prescott & Centrino

Prescott gets 13 new Instructions

What everyone was expecting Louis Burns to talk about was Intel's forthcoming 90nm Pentium 4, codenamed Prescott:

We already knew about the 1MB L2 cache and the 800MHz FSB, but the 13 new instructions was news to us. We're about to find out exactly what those 13 new instructions are, so we'll report on those later today. Another point not mentioned here is that Prescott will have a 16KB L1 data cache, up from the 8KB L1 data cache in the current Northwood processors. The increase in L1 and L2 cache sizes will improve Hyper-Threading performance, although it's not clear as to whether HT performance will improve as a result of other optimizations to the technology in Prescott.

Intel's Louis Burns proudly displaying a massive 300mm Prescott wafer